Dec 16
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QuickLogic’s New Partnership with GLOBALFOUNDRIES Brings Big Benefits

Recently QuickLogic announced that it has joined a cadre of industry leaders in partnering with GLOBALFOUNDRIES for its FDXcelerator™ Program.  (Other members of this program include key technology companies such as Amkor Technology, Mentor Graphics, Rambus, Synopsys, Amkor Technology, ASE Group, Infosys, Mentor Graphics, Rambus, Sasken, Sonics and Cadence.)  The partners will together provide a suite of services enabling SoC developers to rapidly develop their designs targeting a broad class of low-power applications in the IoT, mobile, RF connectivity, and networking markets.

Here’s why the announcement is so important for our customers and other partners.  One of the biggest implications is that this agreement gives QuickLogic access to the GLOBALFOUNDRIES’ 22nm and 12nm FDX™ process technologies.  These technologies provide us with the low cost, low power, and performance we need to continue to deliver world-class discrete FPGA and SoC solutions that embed our FPGA technology.  In particular, these processes will enable us to offer a low-cost migration or a higher-function integration path from the 40nm node and so provide a logical way for us to continue down the process geometry curve.

The 22nm FDX node in particular is well supported by the leading tools vendors, and that fact will help make our transition easier, quicker, and lower cost than it would have been otherwise.  There will be an extensive ecosystem with an open framework in place, enabling us to take advantage of validated, plug-and-play solutions.  The ecosystem includes EDA tools, IP design elements, reference solutions, and outsourced assembly and test capabilities.

Another reason why this partnership matters is our new “embedded FPGA” (or eFPGA) initiative.  This initiative enables companies developing SoCs for any of a wide range of end applications to embed our FPGA technology into their SoC devices.  SoCs with embedded FPGA technology have a number of significant advantages relative to plain vanilla SoCs.

First, they reduce cost by collapsing multi-chip solutions into a single device.  This can often be done almost for free from a die area standpoint as many advanced-node SoC devices are pad limited and so have die area available for additional embedded functionality.  This enables SoC vendors a path to higher average selling prices and gross margins as they can capture more of the semiconductor value.

Second, they increase performance by moving what would have been chip-to-chip connections onto a single die.  The electrical parasitics improve dramatically, and the number of potential connections increases by an order of magnitude or more.  Both factors serve to substantially increase total bandwidth.

Third, the additional design flexibility engendered by SoCs with eFPGA technology allows one device to serve many different applications and markets.  That fact allows the significant development cost of advanced SoCs to be amortized over greater volumes (reducing per unit development costs) and, by driving per-design wafer volumes up substantially, can reduce individual device unit costs.

Thus this new partnership announcement is important both to our current discrete FPGA and SoC customers as we have an assured development path for future families, and for a whole generation of SoC developers who will gain significant cost, performance and flexibility advantages and so are very much looking forward to implementing SoC-with-eFPGA technology.

This entry was posted in Connectivity, Corporate, eFPGA, IoT, Mobile, Sensor Processing Platform and tagged , . Bookmark the permalink. Follow any comments here with the RSS feed for this post. Post a comment or leave a trackback: Trackback URL.

2 Comments

  1. D. House - Jan 26, 2017 @ 1:09 pm | Permalink

    If most SoCs today are pad limited, what percentage ranges of core space of potential GF customers do you think could be available for things like eFPGA?

    If a potential customer already has a GF SoC in active design, can your eFPGA be added in without a major re-design from scratch?

    Lastly, you mentioned 2 years for embedded royalties at Needham. I remember that ASICs used to take 1 year. Did you mean “up to” two years? Is it possible to see royalty revenue in less than 2 years?

    Reply
    • Brian
      Brian (QUICKBLOGGER) - Jan 28, 2017 @ 11:44 am | Permalink

      Great questions, Mr. House.

      Q: If most SoCs today are pad limited, what percentage ranges of core space of potential GF customers do you think could be available for things like eFPGA?
      A: That depends of what the available core area is; there is no straightforward answer for this one. That is why we are building the Borealis eFPGA compiler so that the SoC vendor can build the right size eFPGA to fit into the SoC, even if they are making last minute size changes.

      Q: If a potential customer already has a GF SoC in active design, can your eFPGA be added in without a major re-design from scratch?
      A: Integrating the eFPGA block into an SoC is pretty straightforward. The complexity will be from a system architecture perspective – meaning, how do they tie in the functionality of the eFPGA into the SoC. As long as the SoC vendor has some kind of system bus like AMBA (and they almost always do), then it should be very straightforward to connect the eFPGA as just another IP that the host processor has access to.

      Q: Lastly, you mentioned 2 years for embedded royalties at Needham. I remember that ASICs used to take 1 year. Did you mean “up to” two years? Is it possible to see royalty revenue in less than 2 years?
      A: Less than 2 years is possible, but keep in mind that ASICs/SoCs (especially ones on more aggressive process nodes) can take 1 yr to 18 months to develop, and then there is the time it takes the OEM to adopt the ASIC/SoC into a real system that is produced in volume. So we are planning on around 2 years for first royalties to kick in.

      Reply

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