Back in the good old days of semiconductors (meaning more than one to two decades ago), following Moore’s Law down the process geometry curve gave digital semiconductor companies not only increased logic density, but also lower operating voltages. Five volt supply requirements became 3.3 volts, then 2.5 volts and then 1.8 volts and so on. Since power is partly a function of voltage, the lower supply voltages meant that power consumption per unit of functionality fell accordingly and for a while all was good and right in the world.
However, with the advent of deep sub-micron process geometries and their resulting super-slim gate oxide thicknesses, leakage currents began to creep up and make life more and more difficult for chip designers. At the same time, demand for mobile devices increased exponentially causing consumers to demand dramatically lower device-level power consumption to gain increased batter life.
This dilemma has forced chip architects and designers to get creative. Certain circuit design and layout techniques can mitigate the leakage issue, but not nearly enough to solve the problem completely. To dramatically reduce power consumption, engineers have had to attack the problem more comprehensively. I’ll use QuickLogic’s new EOS 3 Sensor Processing Platform as an example.
In addition to the circuit design techniques mentioned above, we used three main approaches to reduce power consumption. The first was to “harden” certain key functions (see http://www.quicklogic.com/eos for a list) that we knew most users would want, as embedding these functions will always be more power efficient than implementing them in programmable logic. The second was to provide a specialized processor (in the form of our Flexible Fusion Engine) which is more power efficient than a general purpose MCU. The third was to design our sensor algorithms to minimize power consumption through optimal design partitioning across the platform’s M4-F Cortex processor, Flexible Fusion Engine, other embedded functions, and general-purpose programmable logic.
This holistic approach (circuit, architecture, embedded functionality, and efficient algorithm implementation) is the only way to achieve the dramatic level of power reduction required by OEMs to support their most advanced applications and by end customers to support their demanding battery life expectations. Thus a broad system-level approach based on a deep engineering understanding of how the devices works in real applications yields a comprehensive solution which in turn yields lower power consumption and a longer battery life. In other words, knowledge truly is reduced power.