Nov 16
1

Now is the Time for eFPGA Technology

Embedding FPGA technology into SoC designs isn’t really a new idea. In fact, at QuickLogic we’ve been doing it for nearly two decades, starting with our FPGA/hard PCI controller SoC all the way back in 1999. The value proposition was the same then as it is now. Higher levels of integration delivering a higher level of functionality, performance, and design flexibility with lower cost, power consumption, and board space requirements. So why hasn’t eFPGA technology taken off much sooner?

The answer lies fundamentally in the relationship between die costs and development costs. Let’s start with die sizes and costs. Our PCI device in 1999 employed a 0.35 micron process which used 24,650 square microns per logic cell. By 2002, the 180nm process we used for our QuickMIPs device resulted in 9,306 square microns per logic cell – less than half the area for more FPGA capability. Today our latest device, the EOS™ S3 Sensor Processing Platform, includes an even greater level of FPGA capability with a die area of just 961 square microns per logic cell through the use of a 40nm process technology. That’s roughly a factor of 25 reduction in the die area of the eFPGA portion of these devices over the last 18 years.

Lower die area requirements for eFPGA technology mean that it can be integrated into an SoC with only a very minor increase in total device cost. For example, we estimate that in a device built using 40nm process technology, adding 1,000 logic cells of eFPGA capability to a 3mm x 3mm die only increases the total die size by roughly 10%. The corresponding cost increase will be slightly higher or lower percentage-wise depending on die yields and package costs, but the cost increase for such a device is marginal. Given all of the benefits we described earlier, the value proposition from the device perspective now looks really compelling.

Let’s continue on to take a look at development costs. More advanced process technologies are more expensive to develop and require more sophisticated design and verification tools which cost more money and require the SoC designer to invest more time in the design cycle. Making a design error, or getting a feature wrong, or trying to deliver a product extension, or address a group of fragmented but related market opportunities, or keep up with rapidly evolving market requirements all create the need for additional mask spins and that costs significantly more money now than it did ten or twenty years ago.

In today’s world of highly complex SoCs the reality is that the silicon is cheap, but development is expensive.

So what’s a thrifty developer to do? The answer is to embed a reasonable amount of FPGA technology. There will be a relatively small incremental silicon cost, but they will gain the ability to leverage their high investment in development by adding a high degree of post-manufacturing design flexibility. Instead of needing expensive design and verification mask spins to fix bugs, change features, or address new market opportunities or rapidly evolving standards, they will keep the “hard-wired” portion of their device intact and simply update the programmable FPGA portion. In fact, we estimate that a company can very easily save 40% in development costs for two variants of the same design through the use of embedded FPGA technology. And that doesn’t include the higher peak revenue levels, gross margin dollars, and longer time-in-market benefits associated with having the right product in the market at the right time.

If you are an SoC developer or manager, the bottom line is that lower development costs and higher profits are yours for the taking. The time is now.

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One Comment

  1. Joseph - Nov 16, 2017 @ 3:31 pm | Permalink

    Dr. Saxe, where are the sales for EOS3????

    Reply

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